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Two * Commands are provided: one to configure whether or not the cache is enabled at a power-on or reset, and the other to independently turn the cache on or off.
There is also a SWI to turn the cache on or off. A further SWI forces the cache to be flushed. Finally, there is also a set of SWIs that control how various areas of memory interact with the cache.
The default setup is such that all RISC OS programs should run unchanged with the ARM3's cache enabled. Consequently, you are unlikely to need to use the SWIs (beyond, possibly, turning the cache on or off).
A few poorly-written programs may not work correctly with ARM3 processors, because they make assumptions about processor timing or clock rates.
This module is not available in RISC OS 2.00 (ie was introduced in RISC OS 2.01).
For more details of the ARM3 processor, see the Acorn RISC Machine family Data Manual. VLSI Technology Inc. (1990) Prentice-Hall, Englewood Cliffs, NJ, USA: ISBN 0-13-781618-9.
R0 = XOR mask
R1 = AND mask
R0 = old state (0 
CACHEING WAS DISABLED_ 1 cacheing was enabled)
Interrupts are disabled
Fast interrupts are enabled
Processor is in SVC mode
Not defined
This call turns the cache on or off. Bit 0 of the ARM3's control register 2 is altered by being masked with R1 and then exclusive ORd with R0: ie new value = ((old value AND R1) XOR R0). Bit 1 of the control register is also set, so the ARM 3 does not separately cache accesses to the same address for user and non-user modes. (To do so would degrade cache performance, and potentially cause cache inconsistency). Other bits of the control register are set to zero.
None
None
R0 = XOR mask
R1 = AND mask
R0 = old value (bit n set 2MBytes starting at n×2MBytes are cacheable)
Interrupts are disabled
Fast interrupts are enabled
Processor is in SVC mode
Not defined
This call controls which areas of memory may be cached (ie are cacheable). The ARM3's control register 3 is altered by being masked with R1 and then exclusive ORd with R0: ie new value = ((old value AND R1) XOR R0). If bit n of the control register is set, the 2MBytes starting at n×2MBytes are cacheable.
The default value stored is &FC007CFF, so ROM and logical non-screen RAM are cacheable, but I/O space, physical memory, the RAM disc and logical screen memory are not.
None
Controls which areas of memory will be automatically updated in the cache
R0 = XOR mask
R1 = AND mask
R0 = old value (bit n set 2MBytes starting at n×2MBytes are updateable)
Interrupts are disabled
Fast interrupts are enabled
Processor is in SVC mode
Not defined
This call controls which areas of memory will be automatically updated in the cache when the processor writes to that area (ie are updateable). The ARM3's control register 4 is altered by being masked with R1 and then exclusive ORd with R0: ie new value = ((old value AND R1) XOR R0). If bit n of the control register is set, the 2MBytes starting at n×2MBytes are updateable.
The default value stored is &00007FFF, so logical non-screen RAM is updateable, but ROM/CAM/DAG, I/O space, physical memory and logical screen memory are not.
None
Controls which areas of memory cause automatic flushing of the cache on a write
R0 = XOR mask
R1 = AND mask
R0 = old value (bit n set 2MBytes starting at n×2MBytes are disruptive)
Interrupts are disabled
Fast interrupts are enabled
Processor is in SVC mode
Not defined
This call controls which areas of memory cause automatic flushing of the cache when the processor writes to that area (ie are disruptive). The ARM3's control register 5 is altered by being masked with R1 and then exclusive ORd with R0: ie new value = ((old value AND R1) XOR R0). If bit n of the control register is set, the 2MBytes starting at n×2MBytes are disruptive.
The default value stored is &F0000000, so the CAM map is disruptive, but ROM/DAG, I/O space, physical memory and logical memory are not. This causes automatic flushing whenever MEMC's page mapping is altered, which allows programs written for the ARM2 (including RISC OS itself) to run unaltered, but at the expense of unnecessary flushing on page swaps.
Flushes the cache
--
--
Interrupts are disabled
Fast interrupts are enabled
Processor is in SVC mode
Not defined
This call flushes the cache by writing to the ARM3's control register 1.
None
Turns the cache on or off, or gives the cache's current state
*Cache [On|Off]
On or Off
*Cache turns the cache on or off. With no parameter, it gives the cache's current state.
*Cache Off
*Configure Cache
None
Sets the configured cache state to be on or off
*Configure Cache On|Off
On or Off
*Configure Cache sets the configured cache state to be on or off.
*Cache
Games writers may wish to disable the ARM3 cache so that ARM3 based machines run at a similar speed to older ARM2 based machines. You must ensure that your code only tries to call ARM3Support SWIs and * Commands - such as *Cache Off - if the module is present. A simple way to do so is to call the error-returning form of an ARM3Support SWI, and see if an error is returned. For example:
SYS "XCache_Control",0,-1 TO R0;flags IF (flags AND 1) THEN arm3=FALSE ELSE arm3=TRUE IF arm3 THEN *Cache Off